Scan testing has been the foundation of digital-device production test for many years. Several innovations have been developed to keep up with the growth in pattern-set sizes brought about by large ...

There is a rapidly growing interest in the use of structural techniques for testing random logic. In particular, much has been published on new techniques for on-chip compression of automatic test ...

WILSONVILLE, Ore., May 18, 2015 -- Mentor Graphics Corp. (NASDAQ: MENT) today announced that Mellanox Technologies has standardized on the new Mentor® Tessent® Hierarchical ATPG solution to manage the ...

For testing complex chip designs it makes sense to combine the two most common test methodologies -logic built-in self-test (LBIST) and automatic test pattern generation (ATPG), writes Amer ...

The old adage “time is money” is highly applicable to the production testing of semiconductor devices. Every second that a wafer or chip is under test means that the next part cannot yet be tested.

The ability to create and choose the most effective test patterns has become more daunting as more patterns are introduced, says Ron Press of Siemens Digital Industries. Choosing the most efficient ...

There is a rapidly growing interest in the use of structural techniques for testing random logic. In particular, much has been published on new techniques for on-chip compression of automatic test ...