EDN

Testbenches carry same HDL into simulation

San Mateo, Calif. – As the size of the verification problem in system-on-chip design has become apparent, design teams have been throwing any resources they can lay their hands on at the problem.
EDN

Correlating behavioral cycle time with HDL simulation

As total system complexity grows, so does verification complexity. To speed simulation time and improve functional coverage of the RTL ASIC under test, the transactors used for RTL verification must ...
Business Wire

Aldec Brings Assertions to FPGA Designers with the Release of Active-HDL 8.1

HENDERSON, Nev.--(BUSINESS WIRE)--Aldec, Inc., a pioneer in mixed-language simulation for ASIC and FPGA devices, announced today the release of Active-HDL 8.1. The new release introduces a ...
Design-Reuse

Connecting reality and simulation: Couple high speed FPGAs with your HDL simulation

This paper shows a way to connect a FPGA based prototyping environment with a HDL simulator. When the pure cosimulation feature is used, speedups in a range from 2 to 50 are achievable. We show a new ...
Business Wire

Aldec Releases Active-HDL 10.1 with 64-bit Simulation Support

HENDERSON, Nev.--(BUSINESS WIRE)--Aldec, Inc., announces the latest release of its mixed-language FPGA design platform, Active-HDL™ 10.1. Popular with designers for more than 15 years for FPGA design ...
Design-Reuse

Aldec's Active-HDL Verification Capabilities Enhanced to Support SystemVerilog Constructs and UVM

Henderson, USA – December 3, 2019 – Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification for FPGA and ASIC designs, has greatly enhanced the verification ...
Semiconductor Engineering

HDL Simulation Acceleration Solution For Microchip FPGA Designs

A way to accelerate a HDL simulation for a system FPGA design that includes the custom logic and reused IP cores where the testbench executes in the simulator and the synthesizable parts of the design ...
Electronic Design

Facing Up To Today’s FPGA Verification Challenges

Today it is not unusual for FPGA users to have to deal with more than one language in their designs. At earlier stages of the design development it may be necessary to interface HDL simulation with ...
Electronic Design

Breaking News: HDL Design And Simulation Environment

Doubling the performance of the previous release, Version 6.2 of Active-HDL is an integrated, Windows-based HDL design and simulation environment. Behavioral, gate-level, and timing simulation ...
New Electronics

Riviera-PRO supports system simulation of AMD Versal ACAP designs

Aldec, a specialist in mixed HDL language simulation and hardware-assisted verification for FPGA and SoC designs, has announced the latest release of the Riviera-PRO, providing support for system ...
Ars Technica

VHDL / HDL compiler and simulator

A question for any CpE/EE/CS students/grads out there: I am currently using Altera Max-Plus II, but on my windows box only because that is all it supports. However I was wondering if there are any ...