EDN

Product how-to: Achieving STARC and DO-254 compliance using HDL Coder-generated code

HDL Coder generates target independent, synthesizable Verilog and VHDL code from MATLAB functions, Simulink models, and Stateflow charts. The generated HDL code is bit-true and cycle-accurate to ...
Semiconductor Engineering

Verilog HDL And Its Ancestors And Descendants

This paper describes the history of the Verilog hardware description language (HDL), including its influential predecessors and successors. Since its creation in 1984 and first sale in 1985, Verilog ...
Design-Reuse

SmartDV Adds Support for Verilator Open Source HDL Verilog Simulator

SAN JOSE, CALIF. –– October 1, 2019 –– SmartDV™ Technologies today announced support for Verilator, the free, open-source hardware description language (HDL) simulator, becoming the first Verification ...
Design-Reuse

Methodology for protection and Licensing of HDL IP

HDL Intellectual Property commerce depends mainly on two factors: protection of investment and flexibility of usage. These two are diverse factors; the higher is the protection, the lower is the ...
Electronic Design

Verilog-AMS Update Integrates With HDL Standard

The latest version of Accellera’s Verilog-Analog Mixed-Signal (AMS) standard, Verilog-AMS 2.3, unifies the standard’s previous version with IEEE Std. 1364-2005, the Verilog hardware description ...
EDN

A Quick Reference for Verilog HDL

This website offers a nice printable verilog reference. It is a brief summary of the syntax and semantics of the Verilog Hardware Description Language. The summary is not intended at being an ...
Electronic Design

What’s the Difference Between VHDL, Verilog, and SystemVerilog?

Designers of electronic hardware describe the behavior and structure of system and circuit designs using hardware description languages (HDLs)—specialized programming languages commonly known as VHDL, ...