EDN

FPGA IP cores enable flexible SoC design

This product is featured in EDN's Hot 100 products of 2015. See all 100 here. Optimized for TSMC’s 28-nm process, Menta’s predefined off-the-shelf IP cores for complex SoC devices simplify ...
Design-Reuse

Xilinx Accelerates Productivity for Zynq-7000 All Programmable SoCs with the Vivado Design Suite 2014.3, SDK, and New UltraFast Embedded Design Methodology Guide

SAN JOSE, Calif. -- Oct. 8, 2014 -- Xilinx, Inc. (NASDAQ: XLNX) today announced major advances in productivity for Zynq®-7000 All Programmable SoCs with the Vivado® Design Suite 2014.3, the ...
EDN

Isolation Design Flow for Xilinx 7 Series FPGAs or Zynq-7000 AP SoCs

This application note describes how to implement security- or safety-critical designs using the Xilinx® Isolation Design Flow (IDF) with the Xilinx Vivado® Design Suite. Design applications include ...
Hackaday

Xilinx Makes MIPI CSI And DSI Controller IP Blocks Free To Use With Vivado

If you want to use a display or camera with an FPGA, you will often end up with a MIPI-based solution. As of the Xilinx Vivado 2020.1 release, the MIPI DSI (display serial interface) and CSI (camera ...
Design-Reuse

Sidense to Deliver OTP Cores in UMC's 90nm and 65nm Process Nodes

OTP Memory IP Supplier to Provide a Path to Cost Reduction to SoC Designers OTTAWA & HSINCHU, Taiwan--April 25, 2006--Sidense Corp., a provider of One-Time-Programmable (OTP) memory intellectual ...